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|  |
| Abbreviation: | Load: 30(L)
+ 0(E)
+ 0(LE)
+ 0(CE)
|
| Lecturers in charge: | Prof. dr. sc. Joško Radej |
| Lecturers: | |
| Course description: System level integration for System on chip. Executable functional specifications and virtual prototyping. Hardware and software modeling and verification in control, communication and multimedia systems. System architecture definition and IP block selection. Methodology of integrating pre-defined IP blocks in a hierarchical process with timing constraints. Designing semiconductor intellectual properties. IP qualification. IP authoring. Platform based design. |
| Compulsory literature: |
| 1. | Reuse Methodology Manual for System-on-A-Chip Design Keating, Bricaud 2004 |
| 2. | Reuse Techniques for LSI design R. Seepold and A. Kunzman Kluwer Academic Publishers 1999 |
| 3. | The Electronic Design Automation Handbook Dirk Jansen et al. Kluwer Academic Publishing 2003 |
| Recommended literature: - - - |
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